Key Dates

Submission Deadline

May 16, 2016 AoE

Author Notification

June 17, 2016

Paper for Workshop

July 31, 2016

Workshop

August 22/23, 2016

Paper Camera Ready

October 2, 2016

Call for Papers

in text format

Submission

Submit your paper here
(track UCHPC)

Hosting Conference

EuroPar 2016

Previous Workshops

2015 @ EuroPar'15
2014 @ EuroPar'14
2013 @ EuroPar'13
2012 @ EuroPar'12
2011 @ EuroPar'11
2010 @ EuroPar'10
2009 @ CF'09
2008 @ ICCSA'08


Program

The workshop takes place on Tuesday, August 23, 2016 in "Amphitheater 3" of the "Institut Universitaire de Technologie 2" in Grenoble. See also the EuroPar 2016 website.

8:40 Workshop opening
by Josef Weidendorfer, Jens Breitbart
 
8:45 - 10:30 Session 1
Chair: Josef Weidendorfer
8:45 Keynote 1 (more...)
Unconventional Architectures with Reconfigurable Computing (Slides)
by Michaela Blott, Xilinx
9:30 The ICARUS white paper: A scalable, energy-efficient, solar powered HPC center based on low power GPUs (Slides)
by Markus Geveler, Dirk Ribbrock, Hannes Ruelmann, Daniel Donner, Christoph Höppke, Daniel Tomaschewski and Stefan Turek
10:00 Exploiting In-Memory Processing Capabilities for Density Functional Theory Applications (Slides)
by Paul F Baumeister, Thorsten Hater, Dirk Pleiter, Hans Boettiger, Thilo Maurer and José R Brunheroto
 
10:30 (coffee break)
 
11:00 - 12:30 Session 2
Chair: Jens Breitbart
11:00 Theano-MPI: a Theano-based Distributed Training Framework (Slides)
by He Ma, Fei Mao and Graham Taylor
11:30 Acceleration of Turbomachinery Steady Simulations on GPU (Slides)
by Mohamed Hassanine Aissa, Lasse Mueller, Tom Verstraete and Cornelis Vuik
12:00 In-Cache Streaming: Morphable Infrastructure for Many-Core Processing Systems (Slides)
by Nuno Neves, Adrien Mussio, Fabien Gonçalves, Pedro Tomás and Nuno Roma
 
12:30 (lunch break)
 
14:00 - 15:15 Session 3
Chair: Anders Hast
14:00 A low-cost energy-efficient Raspberry Pi cluster for data mining algorithms (Slides)
by João Saffran, Gabriel Garcia, Matheus A. Souza, Pedro H. Penna, Márcio Castro, Luís F. W. Góes and Henrique C. Freitas
14:30 Are Low-Power SoCs Feasible for Heterogenous HPC Workloads? (Slides)
by Max Plauth and Andreas Polze
15:00 Keynote 2 (more...)
Hyperion - A polymorphous high-performance processor introducing novel out-of-order and loop acceleration techniques
by Martin Vorbach, Hyperion Core Inc.
 
15:45 Best Paper Award Ceremony and Workshop Closing

Keynote 1

Michaela Blott (Xilinx Research): Unconventional Architectures with Reconfigurable Computing


Abstract: With Exascale systems on the horizon at the same time that conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy-efficiency, and cooling as first-class constraints concerns for scalable HPC. Reconfigurable logic with FPGAs can tailor the hardware to the application through customized datapaths and memory architectures. Thereby FPGAs can achieve much higher energy efficiencies compared to conventional CPU- and GPU-based solutions. This has stimulated interest in their exploitation within power-hungry data centers with recent benchmarks showing that FPGA-based application acceleration can bring orders of magnitude improvement in regards to performance and performance per Watt compared to their CPU and GPU counterparts. During this talk, we broadly characterize a broad range of applications and hardware architectures in theoretical analysis, leveraging Berkeley's roofline model, as well as report on some of the extensive benchmarking efforts that were conducted within the Xilinx labs in collaboration with numerous university partners and the Irish Centre for High-end Computing (ICHEC).

Michaela Blott graduated from the University of Kaiserslautern in Germany. She worked in both research institutions (ETH and Bell Labs) as well as development organizations and was deeply involved in large scale international collaborations such as NetFPGA-10G. Today, she works as a principal engineer at the Xilinx labs in Dublin heading a team of international researchers, investigating reconfigurable computing for data centers and other new application domains. Her expertise spreads data centers, machine learning, high-speed networking, emerging memory technologies and distributed computing systems, with an emphasis on building complete implementations.

Keynote 2

Martin Vorbach (Hyperion Core Inc.): Hyperion - A polymorphous high-performance processor introducing novel out-of-order and loop acceleration techniques


Abstract: Hyperion is a polymorphous processor core architecture with a scaleable Execution Unit built of an array of Arithmetic Processing Elements. The processor core operates in a variety of modes, for example Out-of-Order or Loop Acceleration. In Loop Acceleration mode the array processes loop bodies fully pipelined and semi-static without requiring instruction fetches after issuing the first iteration. A novel technique for Out-of-Order processing has been implemented, fully exploiting the capabilities of the array. Reorder Buffer and Reservation Stations have been eliminated. The architecture achieves high ILP in all modes, for example in the range of 100 in Loop Acceleration mode and even Out-of-Order processing the ILP is up to over 4 times higher than today’s high performance processors. Streaming and pipelining capabilities in Loop Acceleration Mode allow high data bandwidth. The polymorphous implementation eliminates interfacing and memory issues of heterogeneous system architectures. In comparison to high end FPGA systems the array implementation is significantly more efficient. The array based Out-of-Order technology reduces silicon overhead and consequently power consumption. The Hyperion processor architecture is a breakthrough in programmability: It is fully C/C++ programmable eliminating the obstacles of heterogeneous system architectures.

Martin Vorbach is a worldwide recognized leader in advanced processor architectures. He holds over 110 patents in the areas of FPGA, DSP, superscalar architectures, reconfigurable accelerators and heterogeneous processor architectures. His research had significant impact on modern multi-core processor architectures and heterogeneous data processing systems. His patents are licensed by major semiconductor companies in Europe and the US. He dropped out of the University of Karlsruhe where he studied Computer Science to found PACT XPP Technologies AG and is founder of Hyperion-Core Inc.